FIG. 1 shows a typical flash E.sup.2 PROM cell 10 of the prior art. The cell 10 is made up of a transistor 11 having a substrate 12 of, for example, P type conductivity, with a source 14 and a drain 16 of N type conductivity along a surface of a substrate, the source 14 and drain 16 defining therebetween a channel region 18 along the surface of the substrate 12. Overlying the channel region 18 is an oxide layer 20 on which is disposed a first polysilicon layer 22. The polysilicon layer 22 has disposed thereon an oxide layer 24, which in turn has disposed thereon a second polysilicon layer 26. The polysilicon layer 22 is the floating gate of the device 10, while the polysilicon layer 26 is the control gate thereof.
As is well known, the threshold voltage of the transistor 11 can be changed by addition of electrons to the floating gate 22, or removal of electrons therefrom. In adding electrons to the floating gate 22 (programming the cell), typical of a flash E.sup.2 PROM cell, the control gate 26 and drain 16 are held at a high positive voltage, while the source 14 is held at ground, the voltage being sufficient to bring the transistor 11 into an avalanche condition, so that hot electrons pass through the oxide 20 into the floating gate 22. For removal of electrons from the floating gate 22 (erasing the cell), again typical of a flash E.sup.2 PROM cell, a high positive voltage is applied to the source 14, while the control gate 26 is held at ground, so that electrons are drawn from the floating gate 22 through the oxide 20 to the source 14.
A schematic representation of such a prior art E.sup.2 PROM memory cell is shown in FIG. 2. As noted therein, the bit line BL is connected to the drain 14 of the transistor 10, while the word line WL is connected to the control gate 26.
A prior art array 31 of cells of the type shown in FIGS. 1 and 2 is shown in FIG. 3. The array of FIG. 3 includes for illustrative purposes four such cells 32, 34, 36, 38, each cell including a single transistor as described above. A first bit line BL1 is connected to the drain 14A, 14B of each transistor 11A, 11B in a first column of cells 32, 34, while the source 16A, 16B of each such transistors 11A, 11B is connected to ground. A second bit line BL2 is connected to the drain 14C, 14D of each transistor 11C, 11D in a second column of cells 36, 38, with the source 16C, 16D of each such transistor connected to ground.
The control gates 26A, 26C of the transistors 11A, 11C in a first row of cells 36, 38 are connected to a first word line WL1, while the control gates 26B, 26D of the transistors 11B, 11D in a second row of cells 34, 38 are connected to a second word line WL2.
In programming an individual cell, for example the cell 32, a high positive voltage is applied to word line WL1, while bit line BL1 is also held high and the source 16A is held low, the voltages being sufficiently high to bring the transistor 11A into an avalanche condition, so that hot electrons will travel through the oxide 20 to the floating gate 22A thereof. Meanwhile bit line BL2 and word line WL2 are held low, as are the sources of transistors 11B, 11D.
In such programming, with the bit line BL1 held high, the non-selected cell 34 on the selected bit line, i.e., the transistor 11B, will see a high voltage at the drain 14B thereof, with the source 16B and the word line WL2 low. In order to avoid leakage of the transistor 11B, such a transistor would have to have a very high threshold and/or a very long channel, both of which are detrimental to performance of the device and packing density thereof. If such leakage does occur, it is possible that hot electrons can flow to the floating gate 22B thereof, undesirably changing the threshold voltage of the transistor 11B (called "drain disturbance").
Furthermore, again in regard to, for example, the programming of cell 32, with all high and low conditions as set forth above, with word line WL1 high, even with bit line BL2 low it is possible that electrons will be drawn from the source 14C or drain 16C of the transistor 11C, into the floating gate, undesirably changing the threshold voltage of transistor 11C (called "gate disturbance").